发明名称 Semiconductor device and driving method thereof
摘要 Brightness irregularities that develop in a light emitting device due to is persion among pixels in the threshold values of TFTs used for supplying electric current to light emitting devices become obstacles to improved image quality of the light emitting device. As an image signal input to a pixel from a source signal line, a desired electric potential is applied to a gate electrode of a TFT for supplying electric current to an EL device, through a TFT having its gate and drain connected to each other. A voltage equal to the TFT threshold value is produced between the source and the drain of the TFT 105. An electric potential in which the image signal is offset by the amount of the threshold value is therefore applied to the gate electrode of the TFT. Further, TFTs are disposed in close proximity to each other within the pixel, so that dispersions in the TFT characteristics do not easily develop. A desired drain current can thus be supplied to the EL device even if there is dispersion in the threshold values of the TFTs among pixels, because this is offset by the threshold value of the TFT.
申请公布号 US8896506(B2) 申请公布日期 2014.11.25
申请号 US201113097149 申请日期 2011.04.29
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kimura Hajime;Tanada Yoshifumi
分类号 G09G3/30;G09G3/32;G09G3/20 主分类号 G09G3/30
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a first switch; a second switch; a third switch; a fourth switch; a fifth switch; a capacitor; and an n-channel transistor, wherein a first terminal of the first switch is directly connected to a first line, wherein a second terminal of the first switch is directly connected to a source of the n-channel transistor, wherein a first terminal of the second switch is electrically connected to a drain of the n-channel transistor, wherein a second terminal of the second switch is electrically connected to a second line, wherein a first terminal of the third switch is directly connected to a gate of the n-channel transistor, wherein a second terminal of the third switch is directly connected to the drain of the n-channel transistor, wherein a first terminal of the fourth switch is electrically connected to a load, wherein a second terminal of the fourth switch is electrically connected to a third line, wherein a first terminal of the fifth switch is electrically connected to the source of the n-channel transistor, wherein a second terminal of the fifth switch is electrically connected to the first terminal of the fourth switch, wherein a first terminal of the capacitor is directly connected to the gate of the n-channel transistor, and wherein a second terminal of the capacitor is directly connected to the first terminal of the fourth switch.
地址 Atsugi-shi, Kanagawa-ken JP