发明名称 Trench power MOSFET
摘要 A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
申请公布号 US8896060(B2) 申请公布日期 2014.11.25
申请号 US201213486681 申请日期 2012.06.01
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Ng Chun-Wai;Chou Hsueh-Liang;Liu Ruey-Hsin;Su Po-Chih
分类号 H01L29/78 主分类号 H01L29/78
代理机构 Slater and Matsil, L.L.P. 代理人 Slater and Matsil, L.L.P.
主权项 1. A device comprising: a semiconductor region of a first conductivity type; a trench extending into the semiconductor region; a field plate in the trench, wherein the field plate is conductive; a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region; a main gate in the trench and overlapping the field plate; a second dielectric layer between and separating the main gate and the field plate from each other, wherein the second dielectric layer comprises a bottom surface; a Doped Drain (DD) region of the first conductivity type under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region, and the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer; and a body region comprising a first portion at a same level as a portion of the main gate, and a second portion underlying and contacting the bottom surface of the second dielectric layer, wherein the body region is of a second conductivity type opposite the first conductivity type.
地址 Hisn-Chu TW