发明名称 Semiconductor device and method for manufacturing the same
摘要 In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 μm. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.
申请公布号 US8896111(B2) 申请公布日期 2014.11.25
申请号 US201313795297 申请日期 2013.03.12
申请人 Kabushiki Kaisha Toshiba 发明人 Tanimoto Akira;Imoto Takashi;Ando Yoriyasu;Noda Masashi;Iwamasa Naoki;Miyashita Koichi;Kawato Masatoshi;Iwamoto Masaji;Tanaka Jun;Dohmae Yusuke
分类号 H01L23/02;H01L21/00;H01L23/488;H01L21/50;H01L23/31 主分类号 H01L23/02
代理机构 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A semiconductor device, comprising: a circuit board including a core material having a thermal expansion coefficient in a range of 8 to 10 ppm/° C. and a room temperature modulus of elasticity in a range of 30 to 40 GPa; a first semiconductor chip disposed on the circuit board; an adhesive layer fixing the first semiconductor chip to the circuit board and having a thickness in a range of 95 to 150 μm, a thermal expansion coefficient in a range of 70 to 470 ppm/° C., and a room temperature modulus of elasticity in a range of 2 to 3 GPa; a second semiconductor chip, at least a part of which is embedded in the adhesive layer, having an outer shape smaller than that of the first semiconductor chip; a first connecting member electrically connecting the circuit board and the first semiconductor chip; a second connecting member electrically connecting the circuit board and the second semiconductor chip; and a sealing resin layer provided on the circuit board to seal the first and second semiconductor chips with the first and second connecting members, wherein a thickness of the sealing resin layer on the first semiconductor chip is in a range of 190 to 440 μm.
地址 Tokyo JP