Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors

摘要

The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

主权项

1. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a semiconductor substrate comprising a p-type doping concentration; a gate stack formed above said semiconductor substrate wherein said gate stack comprises a control gate that is formed from a first material and a floating gate that is formed from a second material; a drain side sidewall spacer formed on a drain side of said gate stack; and a source side sidewall spacer formed on a source side of said gate stack wherein the effective channel length of said MOSFET extends from an outer surface of said drain side sidewall spacer formed on said drain side to an outer surface of said source side sidewall spacer formed on said source side and wherein said semiconductor substrate is free of n-type dopants in portions of said substrate underneath and directly contacting said source side sidewall spacer and said drain side sidewall spacer and the doping for an associated source and an associated drain are formed outside of the outside edges of said source and drain side sidewall spacers and does not extend within the outside edges and extends to a surface of the substrate that is coplanar with portions of the substrate that interface the gate stack wherein said control gate is fabricated with a first p-type polysilicon material and wherein said floating gate adjacent to the control gate is fabricated with a second materially different p-type base polysilicon material and separated by said dielectric layer.