| 发明名称 |
Error recovery operations for a hardware accelerator |
| 摘要 |
In at least some embodiments, an apparatus includes a hardware accelerator subsystem with a pipeline. The hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error. The error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point. |
| 申请公布号 |
US8896610(B2) |
申请公布日期 |
2014.11.25 |
| 申请号 |
US201213399372 |
申请日期 |
2012.02.17 |
| 申请人 |
Texas Instruments Incorporated |
发明人 |
Rajendran Resmi;Shastry Pavan Venkata |
| 分类号 |
G06T1/20 |
主分类号 |
G06T1/20 |
| 代理机构 |
|
代理人 |
Marshall, Jr. Robert D.;Telecky, Jr. Frederick J. |
| 主权项 |
1. An apparatus comprising:
a hardware accelerator subsystem with a pipeline, wherein the hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error, wherein the error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point, and wherein, during the overwrite process, ping state commands of the hardware accelerator subsystem are directly overwritten with NOPs by a sequencer component. |
| 地址 |
Dallas TX US |
