Clock Generation Using Fixed Dividers and Multiplex Circuits

摘要

Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

主权项

1. An apparatus, comprising:
a reference clock circuit configured to generate a reference clock; a phase-locked loop (PLL), wherein the PLL is configured to generate the base clock signal; a plurality of clock divider circuits, wherein each clock divider circuit of the plurality of clock divider circuits is configured to divide a frequency of the base clock signal by a respective one of a plurality of divisors; and a multiplex circuit configured to:
receive a plurality of selection signals;select an output of the plurality of clock divider circuits dependent upon the received plurality of selection signals; andcouple the selected output of the plurality of clock divider circuits to a functional block of a computing system.