发明名称 |
OUTPUT VOLTAGE VARIATION REDUCTION |
摘要 |
A method of reducing voltage variations in a power supply may include generating an intermediate voltage and setting a first-transistor gate voltage at a first-transistor gate of a first transistor of the power supply based on the intermediate voltage. The method may also include setting an output voltage at an output node of the power supply based on a second-transistor gate voltage at a second-transistor gate of a second transistor. Additionally, the method may include setting the second-transistor gate voltage based on the first-transistor gate voltage such that the output voltage is based on the intermediate voltage, a first-transistor threshold voltage of the first transistor, and a second-transistor threshold voltage of the second transistor and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out. |
申请公布号 |
US2014340067(A1) |
申请公布日期 |
2014.11.20 |
申请号 |
US201313894275 |
申请日期 |
2013.05.14 |
申请人 |
Intel IP Corporation |
发明人 |
ZHONG Kai;YU Chuanzhao |
分类号 |
G05F3/08 |
主分类号 |
G05F3/08 |
代理机构 |
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代理人 |
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主权项 |
1. A power supply comprising:
a reference node having a reference voltage; an intermediate node having an intermediate voltage; an output node having an output voltage; a voltage regulator configured to generate the intermediate voltage based on the reference voltage; a first transistor having a first-transistor threshold voltage and including a first-transistor source and a first-transistor gate, the first-transistor source communicatively coupled to the intermediate node such that a first-transistor gate voltage at the first-transistor gate is based on the intermediate voltage; and a second transistor having a second-transistor threshold voltage and including a second-transistor source and a second-transistor gate, the second-transistor source communicatively coupled to the output node such that the output voltage is based on a second-transistor gate voltage at the second-transistor gate, the second-transistor gate being communicatively coupled to the first-transistor gate such that the output voltage is based on the intermediate voltage, the first-transistor threshold voltage, and the second-transistor threshold voltage and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out. |
地址 |
Santa Clara CA US |