发明名称 |
Systems and methods for acquiring a received data signal in a clock and data recovery circuit |
摘要 |
<p>A clock a data recovery circuit (CDR) operates recovers data from a serial input signal. The CDR uses oversampling to sample the serial input signal at multiple phases. The multiple phases are generated from a reference clock that is not locked to the data rate of the serial input signal. A maximum of two phases are used at a time. The resulting CDR provides high performance while having low power consumption.</p> |
申请公布号 |
EP2804321(A1) |
申请公布日期 |
2014.11.19 |
申请号 |
EP20140168185 |
申请日期 |
2014.05.13 |
申请人 |
ADEPTENCE, LLC |
发明人 |
LAKKIS, ISMAIL |
分类号 |
H03L7/081;H03L7/07;H04L7/033 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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