Methods and circuits for reducing clock jitter

摘要

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

主权项

1. An integrated circuit comprising:
a data sampler having a data input node, a data output node, and a clock node; a data path extending to the data input node; a clock path extending from a clock source to the clock node and including a continuous-time equalizer, the continuous-time equalizer having an equalization control port; and equalization control circuitry coupled between the data output node and the equalization control port.