发明名称 |
Precision resistor for non-planar semiconductor device architecture |
摘要 |
Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively. |
申请公布号 |
US8889508(B2) |
申请公布日期 |
2014.11.18 |
申请号 |
US201414313678 |
申请日期 |
2014.06.24 |
申请人 |
Intel Corporation |
发明人 |
Yeh Jeng-Ya D.;Vandervoorn Peter J.;Hafez Walid M.;Jan Chia-Hong;Tsai Curtis;Park Joodong |
分类号 |
H01L21/8234;H01L29/66;H01L49/02 |
主分类号 |
H01L21/8234 |
代理机构 |
Blakely, Sokoloff, Taylor & Zafman LLP |
代理人 |
Blakely, Sokoloff, Taylor & Zafman LLP |
主权项 |
1. A method of fabricating a semiconductor structure, the method comprising:
forming first and second semiconductor fins above a substrate; forming a resistor structure above the first semiconductor fin but not above the second semiconductor fin; and forming a transistor structure from the second semiconductor fin but not from the first semiconductor fin, the forming comprising:
forming one or more dummy gates above the second semiconductor fin; and, subsequent to forming the resistor structure,replacing the one or more dummy gates with a permanent gate stack. |
地址 |
Santa Clara CA US |