Jitter generator for generating jittered clock signal

摘要

A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes.

主权项

1. A jitter generator for generating a jittered clock signal, the jitter generator comprising:
a jitter control signal generator configured to select a digital control code from a plurality of candidate digital control codes at individual time points, each of the plurality of candidate digital control codes comprising a digitized arbitrary waveform, and outputting the selected digital control code, the selected digital control code comprising a sequence of consecutively different amplitudes at different time points, wherein the jitter control signal generator comprises:
a direct digital frequency synthesizer (DDFS), configured to generate the digital control code according to a jitter frequency control signal and a jitter amplitude control signal, anda decoder, coupled to the DDFS, configured to decode an output of the DDFS to generate the digital control code; a jittered clock generator, coupled to the jitter control signal generator, configured to deterministically generate the jittered clock signal, wherein the jittered clock generator dynamically provides the jittered clock signal according to the selected digital control code, the generated jittered clock signal comprising jitter over a plurality of contiguous clock cycles, wherein the jittered clock generator comprises:
a multi-phase clock generator, configured to generate a plurality of candidate output clock signals according to an input clock signal wherein the candidate output clock signals have identical frequency and diverse phases; anda phase selector, coupled to the multi-phase clock generator and the phase control signal generator, configured to concurrently receive the plurality of candidate output clock signals and select a respective one of the candidate output clock signals according to the respective different time points to generate the jittered clock signal.