Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths

摘要

Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.

主权项

1. A semiconductor structure comprising:
a first semiconductor region; a second semiconductor region positioned laterally adjacent to said first semiconductor region; and a trench isolation structure laterally surrounding said first semiconductor region and said second semiconductor region such that said first semiconductor region is electrically isolated from said second semiconductor region,
said first semiconductor region having first end portions and a first center portion positioned laterally between said first end portions, said first center portion being narrower than said first end portions and having a first width, andsaid second semiconductor region having second end portions and a second center portion positioned laterally between said second end portions, said second center portion being narrower than said second end portions and having a second width that is less than said first width.