Methods and apparatus for packing received frames in buffers in a serial attached SCSI (SAS) device

摘要

Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA staging buffer for transmission to a host's system buffer memory using DMA features of the SAS device. The DMA circuit is programmed and started when the staging buffer is filled to at least a threshold amount of data to thereby improve efficacy of the DMA transfer performance. Other criteria may also be employed to determine when to start the DMA circuit.

主权项

1. An apparatus in a Serial Attached SCSI (SAS) device configured to buffer data for transmission to a system buffer memory of an attached host device, the apparatus comprising:
a frame buffer memory adapted to store frames as they are received from another SAS device wherein received frames each comprise one or more of: user data and data integrity field (DIF) information for validating user data; a direct memory access (DMA) staging buffer memory adapted to store user data derived from received frames for transmission to a system buffer memory in a system coupled with the SAS device; a DMA circuit coupled with the DMA staging buffer memory and adapted to controllably transfer user data from the DMA staging buffer memory to the system buffer memory; an end to end data protection (EEDP) circuit coupled with the frame buffer memory and adapted to validate user data in a received frame using associated DIF information in a received frame; and control logic coupled with the EEDP circuit and with the DMA circuit and with the frame buffer memory and with the DMA staging buffer memory, the control logic adapted to, responsive to the EEDP circuit validating user data in a received frame, eliminate DIF information associated with the valid user data, and copy the valid user data from the frame buffer memory into the DMA staging buffer memory contiguous with other valid user data, such that the DMA staging buffer includes valid user data without including DIF information, the control logic further adapted to start the DMA circuit to send valid user data in the DMA staging buffer memory to the system buffer memory responsive to sensing that the amount of valid user data in the DMA staging buffer memory exceeds a predetermined threshold value.