Glitch-free input transition detector

摘要

A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

主权项

1. A circuit for detecting a signal transition on an input signal, the circuit comprising:
an input signal path configured to receive an input signal on an input node and to provide a buffered input signal to an output node as an output signal; an input transition detector configured to receive the output signal and to generate a transition detection output signal having one or more detection pulses, each detection pulse being generated in response to a signal transition detected on the output signal; a mirror delay circuit configured to receive a first signal related to the input signal and to generate a second signal being the first signal delayed by a delay time, the mirror delay circuit further configured to generate a third signal based on the first signal and the second signal, the third signal being asserted in response to the first signal and the second signal having the same logical state and being deasserted in response to the first signal and the second signal having different logical states; an input blocking circuit configured to receive the third signal and the transition detection is output signal and to generate a switch control signal based on the third signal and the transition detection output signal, the switch control signal being asserted in response to the third signal being asserted and the transition detection output signal being deasserted, and the switch control signal being deasserted in response to the third signal being deasserted or the transition detection output signal being asserted; and the input block circuit comprising a switch coupled to the input signal path and controlled by the switch control signal, the switch being open in response to the switch control signal being deasserted to block a signal transition on the input signal to be passed to the output node, and the switch being closed in response to the switch control signal being asserted to pass a signal transition on the input signal to the output node.