| 摘要 |
A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device. |
| 主权项 |
1. A computer readable media including computer executable instructions which, when run on a computer, implement a method comprising:
providing, by a test processor, one or more adjustable timing signals to a programmable logic device; implementing, by the programmable logic device, a sequence of states dependent on one or more input signals received from a device under test via a pin electronic circuit interface; acquiring, by the programmable logic device, an output signal dependent on a current or previous sequence state in response to the one or more received input signals, wherein the output signal is indicative of a signal to be output by the pin electronics circuit interface to the device under test; and adjusting, by the test processor, a timing used in a signal processing path through the programmable logic device used to acquire the output signal, wherein the timing is adjusted in response to at least one of the one or more adjustable timing signals. |
