| 摘要 |
When the branch condition of a branch command for a loop process is satisfied and enters the loop mode, the relative branch address is saved in a branch relative address save circuit that points to the branch command for loop processing, and the loop state flag is set in a loop state save circuit. When the loop state flag is set, if the absolute value of the value outputted by a command code counter circuit matches the absolute value of the relative branch address outputted by the branch relative address save circuit, a program counter sum value switching circuit outputs the relative branch address to an program counter adder. If the absolute values do not match, the program counter sum value switching circuit outputs the value ‘1’ to the program counter adder. With this, the branch penalty during loop processing is eliminated even with little hardware. |
| 主权项 |
1. A digital signal processor, comprising: a data memory which stores data as targets for executing processing; a computing unit which executes calculations on the data; a register which temporarily stores results of the calculations; and a program control circuit which generates a control signal that shows an action command for the computing unit, wherein:
the program control circuit comprises a command memory which stores command codes in which commands to be executed by the computing unit are written, a command decoder which sequentially reads out the command codes stored in the command memory and outputs those to the computing unit, and a command memory address generation circuit which generates a command memory address at which a command to be read out from the command memory is stored; the command decoder comprises a circuit for switching branch command for loop processing, which outputs a branch relative address that shows a relative position between an address of a loop processing branch command showing a branch condition of the loop processing and a branch destination address when the command codes are the loop processing in which a same command is sequentially repeated; and the command memory address generation circuit comprises a program counter which outputs addresses on the command memory to the command decoder, a loop state save circuit which saves a loop state flag showing that the loop processing is being executed, a command memory address generation control circuit which sets the loop state flag to the loop state save circuit when the loop processing is being executed, a branch relative address save circuit which saves the branch relative address, a command code length counter circuit which counts a command code length that is a code length of one-time execution of the loop processing, and a program counter sum value switching circuit which outputs, to the program counter, a head address of the loop processing calculated by adding the command code length and the branch relative address when the loop state flag is set and the command code length counter circuit detects a last address of the loop processing, wherein the command detector includes a loop state removal circuit which releases the loop state flag of the loop state save circuit when the branch condition is not satisfied in the loop processing branch command or when the branch condition is satisfied in other branch command. |
