SYSTEMS AND METHODS FOR ACQUIRING A RECEIVED DATA SIGNAL IN A CLOCK AND DATA RECOVERY CIRCUIT

摘要

A clock a data recovery circuit (CDR) operates recovers data from a serial input signal. The CDR uses oversampling to sample the serial input signal at multiple phases. The multiple phases are generated from a reference clock that is not locked to the data rate of the serial input signal. A maximum of two phases are used at a time. The resulting CDR provides high performance while having low power consumption.

主权项

1. A data recovery circuit, comprising:
a Phase Lock Loop (PLL) configured to generate a plurality of clock phase signals; a phase select module configured to produce a first clock signal and a second clock signal from the plurality of clock phase signals, the first and second clock signals for use in acquiring and tracking a received data signal; a first sample generation block configured to generate a first sample of the received data signal under control of the first clock signals; a second sample generation block configured to generate a second sample of the received data signal under control of the second clock signal; and a control module coupled with the first and second sample generation block and the phase select module and configured to control the phase select module so as to iteratively produce the first and second clock signals from pairs of the plurality of clock phase signals and compare the first and second samples to acquire the received data signal.