发明名称 |
Storage device and driving method thereof |
摘要 |
An object is to provide a highly integrated storage device which can operate at high speed and a driving method thereof. The storage device includes two storage portions, two precharge switches, and one sense amplifier. In each of the storage portions, storage elements are arranged in a matrix. In each of the storage elements, a node electrically connected to a source or a drain of a transistor whose off-state current is small is a memory storing portion. A page buffer circuit is unnecessary; thus, high-speed operation is possible and high integration is achieved. |
申请公布号 |
US8885437(B2) |
申请公布日期 |
2014.11.11 |
申请号 |
US201213690483 |
申请日期 |
2012.11.30 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Matsuzaki Takanori |
分类号 |
G11C8/00;G11C11/24;G11C11/405;G11C7/12;G11C11/403;H01L27/108;H01L27/115;G11C16/04;H01L27/12 |
主分类号 |
G11C8/00 |
代理机构 |
Fish & Richardson P.C. |
代理人 |
Fish & Richardson P.C. |
主权项 |
1. A driving method of a storage device comprising a first memory cell and a second memory cell, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first bit line, wherein the other of the source and the drain of the first transistor is electrically connected to a first source line, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line, wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a second bit line, wherein the other of the source and the drain of the third transistor is electrically connected to a second source line, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line, and wherein a first electrode of the second capacitor is electrically connected to the gate of the third transistor, the driving method comprising the steps of:
supplying a first potential to the first source line; supplying a second potential to the first bit line; electrically isolating the first bit line after supplying the second potential to the first bit line; changing a potential of a second electrode of the first capacitor from a third potential to a fourth potential so that the first potential or the second potential is supplied to the first bit line; supplying a fifth potential lower than the second potential to the second bit line; supplying a sixth potential or a seventh potential to the first bit line in accordance with the potential of the first bit line; and turning on a switch provided between the first bit line and an input-output line to read out data of the first bit line. |
地址 |
Kanagawa-ken JP |