Reducing variation in multi-die integrated circuits

摘要

A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.

主权项

1. A method of reducing variation in multi-die integrated circuits, the method comprising:
testing each of a plurality of dies in wafer form during manufacturing for at least one of static power dissipation or operating frequency resulting in test data stored in a memory; for each of the plurality of dies, determining at least one performance metric from the test data using a processor; sorting each of the plurality of dies into one of a plurality of die groups according to the at least one performance metric of each die; and selecting, via the processor, at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric; wherein selecting at least two dies comprises selecting at least two dies from at least one of the plurality of die groups.