发明名称 ON TIME SAMPLING PREVENTION
摘要 An example controller circuit includes a feedback sampling circuit, an oscillator, a drive logic, and a false sampling prevention circuit. The feedback sampling circuit generates a sample signal in response to a sampling of a feedback signal. The oscillator generates an on-time signal that transitions from a first logic state to a second logic state during each period of the on-time signal. The drive logic controls a switch to regulate the output of a power converter. The drive logic turns on the switch to end an off-time of the switch in response to the on-time signal transitioning from the first logic state to the second logic state. The false sampling prevention circuit prevents the on-time signal from transitioning from the first logic state to the second logic state to extend the off-time of the switch until a sampling complete signal indicates that sampling of the feedback signal is complete.
申请公布号 US2014328089(A1) 申请公布日期 2014.11.06
申请号 US201414335637 申请日期 2014.07.18
申请人 Power Integrations, Inc. 发明人 Gaknoki Yury;Kung David;Zhang Michael Yue
分类号 H02M3/335 主分类号 H02M3/335
代理机构 代理人
主权项 1. A controller circuit for use in a power converter having a switch, the controller circuit comprising: a feedback sampling circuit coupled to generate a sample signal in response to a sampling of a feedback signal that is representative of an output of the power converter; an oscillator coupled to generate a periodic on-time signal that transitions from a first logic state to a second logic state; a drive logic to be coupled to control switching of the switch to regulate the output of the power converter in response to the sample signal and in response to the on-time signal, wherein the drive logic is configured to turn on the switch in response to the on-time signal transitioning from the first logic state to the second logic state; and a false sampling prevention circuit coupled to receive a sampling complete signal and coupled to the oscillator to prevent the on-time signal from transitioning from the first logic state to the second logic state until the sampling complete signal indicates that the sampling of the feedback signal is complete.
地址 San Jose CA US
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