METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING

摘要

Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

主权项

1. A three-dimensional memory array comprising:
a memory array layer including an array and a plurality of memory lines wherein portions of the memory lines extend from the array substantially parallel to each other, wherein a first subset of the memory lines extend from a first side of the array, wherein a second subset of the memory lines extend from a second side of the array, wherein within the first subset of memory lines a first plurality of memory lines terminate proximate an edge of the array, wherein within the first subset of memory lines a second plurality of memory lines extend beyond the edge of the array into a contact region, wherein the contact region includes a plurality of contacts adapted to couple the second plurality of memory lines to support circuitry, wherein the contacts are disposed in two or more rows, the contact rows disposed substantially non-parallel to the memory lines, and wherein adjacent memory lines couple to contacts in different rows.