SEMICONDUCTOR MEMORY DEVICES

摘要

A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

主权项

1. A semiconductor memory device comprising:
a memory cell array; a data inversion/mask interface configured to receive a data block including a plurality of unit data, each of the plurality of unit data having a first data size, the data inversion/mask interface configured to selectively enable each data mask signal associated with each of the plurality of unit data based on a number of data bits having a first logic level in a portion of each of the plurality of unit data, the portion having a second data size, and the second data size being smaller than the first data size; and a write circuit configured to receive the data block and configured to perform a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.