发明名称 SINGLE FEEDBACK LOOP FOR PARALLEL ARCHITECTURE BUCK CONVERTER LDO REGULATOR
摘要 <p>An embodiment of a voltage regulation circuit includes a DC-DC converter configured to control a first current provided from a source to a load via a first output, and a linear regulator configured to control a second current provided from the source to the load via a second output. The voltage regulation circuit further includes a single control loop configured to receive an output voltage across the load and a first reference voltage. The single control loop is further configured to generate a single error signal between the output voltage across the load and the first reference voltage and to control the DC-DC converter and the linear regulator using the single error signal such that when the single error signal is outside of a predetermined range the DC-DC converter provides the first current to the load and the linear regulator provides the second current to the load simultaneously.</p>
申请公布号 EP2798729(A1) 申请公布日期 2014.11.05
申请号 EP20120813367 申请日期 2012.12.21
申请人 ST-ERICSSON SA 发明人 MARTY, NICOLAS
分类号 H02M1/00;H02M3/02 主分类号 H02M1/00
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