Method of forming PN floating gate non-volatile storage elements and transistor having N+ gate

摘要

Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

主权项

1. A method for forming a memory array comprising:
forming insulator over a substrate, the insulator formed in one or more first regions for non-volatile storage elements and in one or more second regions for transistors; forming a P− semiconductor region over the insulator in the one or more first regions and in the one or more second regions; forming a first N+ semiconductor region over the P− semiconductor region in the one or more first regions and in the one or more second regions; transforming the P− semiconductor region in the one or more second regions into a second N+ semiconductor region; forming floating gates for non-volatile storage elements in the one or more first regions from the P− semiconductor region and the first N+ semiconductor region that remains in the one or more first regions; and forming transistor gates in the one or more second regions, the transistor gates including portions of the second N+ semiconductor region and portions of the first N+ semiconductor region in the one or more second regions.