发明名称 Methods of manufacturing vertical structure nonvolatile memory devices
摘要 A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.
申请公布号 US8877591(B2) 申请公布日期 2014.11.04
申请号 US201314092191 申请日期 2013.11.27
申请人 Samsung Electronics Co., Ltd. 发明人 Choe Byeong-in;Chang Sung-il;Kang Chang-seok;Lim Jin-soo
分类号 H01L21/336;H01L29/78;G11C16/04;H01L29/66;H01L29/792;H01L27/115;H01L29/788 主分类号 H01L21/336
代理机构 Myers Bigel Sibley & Sajovec, P.A. 代理人 Myers Bigel Sibley & Sajovec, P.A.
主权项 1. A method of manufacturing a vertical structure nonvolatile memory device, comprising: forming a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked on a substrate; forming a channel hole exposing the substrate by etching the plurality of interlayer insulating layers and the plurality of sacrificial layers; forming a channel layer on a sidewall of the channel hole; forming an opening exposing the substrate by etching the plurality of interlayer insulating layers and the plurality of sacrificial layers, the opening being spaced apart from the channel hole; removing the plurality of sacrificial layers through the opening to form a plurality of trenches between two adjacent ones of the plurality of interlayer insulating layers, the plurality of trenches exposing the channel layer; forming a gate insulating layer on inner surfaces of the plurality of trenches; and forming a plurality of gate electrodes on the gate insulating layer in respective ones of the plurality of trenches, a sidewall of one of the plurality of gate electrodes comprising a recess facing the channel layer.
地址 KR