发明名称 |
Method of pattern recognition for artificial intelligence |
摘要 |
Invention for pattern recognition and artificial intelligence comprising:
1) storing data in parallel by applying a logic level (1) input or a logic level (0) input to one input of each of at least two exclusive-nor logic gates;2) comparing data in parallel by applying a logic level (1) input or a logic level (0) input to the other input of each of the exclusive-nor gates, wherein each exclusive-nor gate produces a logic level (1) output when both inputs have the same datum input, and each exclusive-nor gate produces a logic level (0) output when both inputs have different datum input; and3) measuring the outputs of the exclusive-nor logic gates collectively with a measuring apparatus, wherein the percentage of the pattern input for comparison which matches the pattern of data stored in the exclusive-nor gates is directly proportional to the magnitude of the collective output of the exclusive-nor gates. |
申请公布号 |
US8880453(B2) |
申请公布日期 |
2014.11.04 |
申请号 |
US201213563843 |
申请日期 |
2012.08.01 |
申请人 |
|
发明人 |
Snyder Steven Howard |
分类号 |
G06F17/00;G06N5/02;G06K9/00;G06F7/60;G06F7/02;G06F7/501 |
主分类号 |
G06F17/00 |
代理机构 |
|
代理人 |
|
主权项 |
1. Method of pattern recognition comprising the steps of:
1) inputting a pattern of data with the application of input selected from the group consisting of the presence of electrical input comprising a binary logic level 1 input and the absence of electrical input comprising a binary logic level 0 input into one input of each of at least two exclusive-nor logic circuits, wherein a pattern of data is stored; 2) inputting a pattern of data for comparison with the stored pattern of data with the application of input selected from the group consisting of the presence of electrical input comprising a binary logic level 1 input and the absence of electrical input comprising a binary logic level 0 input into the other input of each of the exclusive-nor logic circuits, wherein each exclusive-nor circuit produces output selected from the group consisting of the presence of electrical output comprising a binary logic level 1 output when both inputs have the same datum input and the absence of electrical output comprising a binary logic level 0 output when both inputs have different datum input; and 3) measuring the outputs of the exclusive-nor logic circuits collectively with a measuring apparatus, wherein the percentage of the pattern of data input for comparison which matches the pattern of data stored in the exclusive-nor circuits is directly proportional to the magnitude of the collective output of the exclusive-nor circuits. |
地址 |
|