| 发明名称 |
BUFFER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT |
| 摘要 |
A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock, and an adjustment circuit section adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of the measurement result of the measurement circuit section. |
| 申请公布号 |
US2014320187(A1) |
申请公布日期 |
2014.10.30 |
| 申请号 |
US201414256815 |
申请日期 |
2014.04.18 |
| 申请人 |
FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
INAGAWA Ryoichi |
| 分类号 |
H03K5/156 |
主分类号 |
H03K5/156 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A buffer circuit comprising:
a buffer circuit section which receives an input clock, and outputs an output clock by wave-shaping the input clock; a measurement circuit section which measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock; and an adjustment circuit section which adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of a measurement result of the measurement circuit section. |
| 地址 |
Yokohama-shi JP |
