发明名称 HYBRID INTEGRATION OF GROUP III-V SEMICONDUCTOR DEVICES ON SILICON
摘要 <p>Photonic passivation layers, III-V semiconductor die with offcut edges, and NiGe contact metallization for silicon-based photonic integrated circuits (PICs). In embodiments, a non-sacrificial passivation layer is formed on a silicon photonic element, such as a waveguide for protection of the waveguide surfaces. In embodiments, a III-V semiconductor film is transferred from a III-V growth substrate that is singulated along streets that are misaligned from cleave planes to avoid crystallographic etch artifacts in a layer transfer process. In embodiments, a NiGe contact metallization is employed for both p-type and n-type contacts on a device formed in the transferred III-V semiconductor layer to provide low specific contact resistance and compatibility with MOS processes.</p>
申请公布号 EP2795675(A1) 申请公布日期 2014.10.29
申请号 EP20110878060 申请日期 2011.12.20
申请人 INTEL CORPORATION 发明人 HECK, JOHN;BAR, HANAN;FESHALI, AVI;FELDESH, RAN
分类号 H01L27/14;G02B6/12 主分类号 H01L27/14
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