Thread synchronization in a multi-thread, multi-flow network communications processor architecture

摘要

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A thread status table has N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, a thread indicator and a flow indicator. A sequence counter generates a sequence value for each data flow of each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed. Instructions are processed in the order in which the threads were started for each data flow.

主权项

1. A packet classification processor for a network processor having a plurality of processing modules and at least one shared memory, wherein the network processor generates one or more tasks corresponding to each of a plurality of received packets, the packet processor comprising:
a scheduler configured to generate one or more contexts corresponding to tasks received by the packet classification processor from corresponding ones of the plurality of processing modules, each context corresponding to a given flow; a multi-thread instruction engine configured to process one or more threads of instructions, each thread of instructions corresponding to a context received from the scheduler; a thread status manager configured to maintain:
(i) a thread status table having N status entries, configured to track up to N active threads, where N is a positive integer, and wherein each status entry corresponds to an active thread, and each status entry comprises a valid status indicator, a sequence value, a thread indicator value, and a flow indicator value, and(ii) a sequence counter configured to generate a sequence value for each thread of each flow, wherein the sequence counter is incremented each time processing of a thread for a flow is started by the multi-thread instruction engine, and the sequence counter is decremented each time a thread for a flow is completed by the multi-thread instruction engine, whereby a lower relative sequence value indicates an earlier started thread for each flow; wherein the scheduler is configured to schedule instructions for processing by the packet processor in the order in which the threads were started for each flow, without head-of-line blocking between flows.