发明名称 Sensor pixels, arrays and array systems and methods therefor
摘要 One sensor pixel includes amplifying transistor, coupled between first bias line and data line; switch transistor, operated by control line and coupled between data line and gate of amplifying transistor; storage capacitor, coupled to second bias line; and sensor being coupled to gate of amplifying transistor. Another sensor pixel includes first amplifying transistor coupled between first bias line and data line; second amplifying transistor being coupled between second bias line and data line; switch transistor being operated by control line and being coupled between data line and gates of first and second amplifying transistors; storage capacitor coupled to gates of first and second amplifying transistors; and sensor coupled to gates of first and second amplifying transistors. Trap-assisted absorption, variable capacitor described for sensor pixels, and also biasing to reduce flicker and aging, and to compensate for aging, described for sensor pixels.
申请公布号 US8872095(B2) 申请公布日期 2014.10.28
申请号 US201314096572 申请日期 2013.12.04
申请人 发明人 Nathan Arokia;Chaji G. Reza
分类号 G01J1/44;G01D5/14;H01L27/146;H01L27/148;H01L31/04;G01R27/26;G01J1/46;H04N5/357;G01D5/24;H04N5/378 主分类号 G01J1/44
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. A sensor pixel, comprising: an amplifying transistor having a first terminal, a second terminal and a gate terminal, the first terminal of the amplifying transistor being coupled to a first bias line; a switch transistor having a first terminal, a second terminal and a gate terminal, the gate terminal of the switch transistor being operated by a control line; a storage capacitor having a first terminal and a second terminal, the first terminal of the storage capacitor being coupled to a second bias line; and a sensor, the second terminal of the amplifying transistor and the first terminal of the switch transistor being coupled to at least one data line, and the sensor, the second terminal of the storage capacitor, the second terminal of the switch transistor being coupled to the gate terminal of the amplifying transistor.
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