发明名称 |
Communication interface device |
摘要 |
A sampler samples a receive signal received via a dedicated communication line. A data transfer rate adjuster measures a data transfer rate based on a number of start bit samples contained in the receive signal. A bit determiner makes a bit determination regarding the receive signal at the data transfer rate measured by the data transfer rate adjuster, to thereby acquire serial data contained in the receive signal. A transmitter sends, via the dedicated communication line, a transmit signal containing serial data sent by an MPU. An MPU communicator outputs to the transmitter the serial data sent by the MPU, and outputs to the MPU the serial data acquired by the bit determiner. The data transfer rate adjuster adjusts, when the transmitter sends the transmit signal multiple times at different data transfer rates, the data transfer rate based on the receive status of respective response signals thereto. |
申请公布号 |
US8873607(B2) |
申请公布日期 |
2014.10.28 |
申请号 |
US201113977164 |
申请日期 |
2011.01.27 |
申请人 |
Mitsubishi Electric Corporation |
发明人 |
Endo Satoshi;Koizumi Yoshiaki;Higuma Toshiyasu;Mukai Takuya |
分类号 |
H04B1/38;H04L25/02;H04L12/64 |
主分类号 |
H04B1/38 |
代理机构 |
Posz Law Group, PLC |
代理人 |
Posz Law Group, PLC |
主权项 |
1. A communication interface device for a processor, comprising:
a sampler that samples a receive signal received via a communication line; a data transfer rate acquirer that acquires a data transfer rate; a bit determiner that makes a bit determination regarding the receive signal at the acquired data transfer rate acquired by the data transfer rate acquirer, to thereby acquire serial data contained in the receive signal; a transmitter that sends, via a communication line at the acquired data transfer rate acquired by the data transfer rate acquirer, a transmit signal containing serial data sent by the processor; a processor communicator that outputs to the transmitter the serial data sent by the processor, and outputs to the processor the serial data acquired by the bit determiner; and an adjuster that, when the transmitter sends the transmit signal multiple times at different data transfer rates, adjusts the data transfer rate based on the receive status of respective response signals thereto. |
地址 |
Tokyo JP |