发明名称 Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate
摘要 Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.
申请公布号 US8871635(B2) 申请公布日期 2014.10.28
申请号 US201213466895 申请日期 2012.05.08
申请人 GLOBALFOUNDRIES, Inc. 发明人 Park Chanro;Ryan Errol T.
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 Ingrassia Fisher & Lorenz, P.C. 代理人 Ingrassia Fisher & Lorenz, P.C.
主权项 1. A process for forming an integrated circuit, the process comprising: providing a substrate comprising an oxide layer and a protecting layer disposed over the oxide layer; etching a recess through the protecting layer and at least partially into the oxide layer; depositing a barrier material in the recess to form a barrier layer over the protecting layer and the oxide layer in the recess; depositing an electrically-conductive material different from the barrier material over the barrier layer in the recess to form an embedded electrical interconnect; recessing the embedded electrical interconnect to an interconnect recess depth within the substrate; recessing the barrier layer to a barrier recess depth within the substrate after recessing the embedded electrical interconnect, wherein at least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer; removing the protecting layer from the oxide layer after recessing the barrier layer; and forming a capping layer within the recess directly over the embedded electrical interconnect and the barrier layer that have been recessed, and directly over the oxide layer after removing the protecting layer from the oxide layer, wherein the capping layer comprises dielectric material.
地址 Grand Cayman KY