| 发明名称 | Digital front end receiver using DC offset compensation scheme | ||
| 摘要 | The present invention relates to a digital front end receiver using a DC offset compensation scheme. The digital front end receiver includes a DC offset compensation filter configured to remove DC offset components from signals received from a digital mixer and a Cascaded Integrator-Comb (CIC) decimation filter configured to reduce a sampling rate of the signals received from the DC offset compensation block. | ||
| 申请公布号 | US8873687(B2) | 申请公布日期 | 2014.10.28 |
| 申请号 | US201213609704 | 申请日期 | 2012.09.11 |
| 申请人 | Electronics and Telecommunications Research Institute | 发明人 | Kim Sang-Kyun;Eo Ik Soo;Yu Hyun Kyu |
| 分类号 | H04B1/10;H04B1/00 | 主分类号 | H04B1/10 |
| 代理机构 | Rabin & Berdo, P.C. | 代理人 | Rabin & Berdo, P.C. |
| 主权项 | 1. A digital front end receiver using a DC offset compensation scheme, comprising: a DC offset compensation filter configured to remove DC offset components from signals received from a digital mixer; and a Cascaded Integrator-Comb (CIC) decimation filter configured to reduce a sampling rate of the signals received from the DC offset compensation filter, wherein the DC offset compensation filter calculates an average of the input signals for previously set N samples and estimates the DC offset components included in the input signals based on the calculated average, and wherein the DC offset compensation filter estimates the DC offset components in response to an enable signal enabled once for each m clock (wherein m is a natural number greater than 1) of a real operating clock. | ||
| 地址 | Daejeon KR | ||