发明名称 Wafer testing system and associated methods of use and manufacture
摘要 A wafer testing system and associated methods of use an manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.
申请公布号 US8872533(B2) 申请公布日期 2014.10.28
申请号 US201313849887 申请日期 2013.03.25
申请人 Advanced Inquiry Systems, Inc. 发明人 Durbin Aaron;Keith David;Johnson Morgan
分类号 G01R31/26;G01R1/04;G01R1/073;G01R31/28 主分类号 G01R31/26
代理机构 Perkins Coie LLP 代理人 Perkins Coie LLP
主权项 1. A wafer testing system, comprising: an interposer having a first surface and a second surface facing away from the first surface, wherein at least one contact pad at the first surface is electrically connected with at least one contact pad at the second surface; a wafer translator having: a substrate having a first side facing the interposer and a second side facing away from the first side, the second side positioned to face toward a wafer,a first terminal at the first side,a second terminal at the second side, positioned to contact a corresponding wafer terminal, wherein the first terminal is larger than the second terminal, andan electrical pathway connecting the first and second terminals; and a translator support configured to receive the wafer translator, the translator support having a seal configured to seal a space between the wafer translator and the interposer.
地址 Beaverton OR US