发明名称 VERIFICATION ITEM EXTRACTION DEVICE AND VERIFICATION ITEM EXTRACTION METHOD
摘要 PROBLEM TO BE SOLVED: To efficiently set the priority order of items of verification performed by logic simulation of a semiconductor integrated circuit.SOLUTION: A verification item extraction device includes a storage unit and a priority determination unit. The storage unit stores description data in which the operation of a verification target circuit is described. The priority determination unit derives a connection relation of input/output for each logic in the verification target circuit, on the basis of connection information obtained from the description data of the storage unit; determines a first priority for verifying the logic on the basis of the derived connection relation; extracts a related I/F that is an interface with the outside for input to the logic, on the basis of the connection information; and determines a second priority for verifying the related I/F, on the basis of the first priority.
申请公布号 JP2014203296(A) 申请公布日期 2014.10.27
申请号 JP20130079691 申请日期 2013.04.05
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 TANIGAWA MOTOYA;IKEDA NORIYUKI;WATANABE GYOJI;TANOWAKI JUN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址