DATA PROCESSING APPARATUS AND METHOD FOR PRE-DECODING INSTRUCTIONS TO BE EXECUTED BY PROCESSING CIRCUITRY

摘要

A hierarchical cache with at least a unified cache is used to store both instructions and data values, and a further cache coupled between processing circuitry and a unified cache. The unified cache has a plurality of cache lines identified as an instruction cache line or a data cache line. Each data cache line stores at least one data value and the associated information. Pre-decode circuitry is associated with the unified cache and performs a first pre-decode operation on a received instruction for that instruction cache line in order to generate a corresponding partially pre-decoded instruction for storing in the instruction cache line. Further pre-decode circuitry is associated with the further cache, and, when a partially pre-decoded instruction is routed to the further cache, performs a further pre-decode operation on the partially pre-decoded instruction to generate a corresponding pre-decoded instruction for storage in the further cache.

主权项

1. A data processing apparatus comprising:
processing circuitry configured to execute instructions fetched from memory in order to perform processing operations on data values; a hierarchical cache structure configured to store the instructions fetched from said memory for access by the processing circuitry, the hierarchical cache structure comprising at least a unified cache configured to store both instructions and data values and a further cache coupled between the processing circuitry and the unified cache; the unified cache having a plurality of cache lines, each cache line being identified as an instruction cache line or a data cache line and each cache line having an associated information portion; each data cache line being configured to store at least one data value and the associated information portion being configured to store error correction code (ECC) data used for error detection and correction within that data cache line's stored content; pre-decode circuitry associated with the unified cache and configured, for each instruction cache line, to perform a first pre-decode operation on at least one received instruction for that instruction cache line in order to generate at least one partially pre-decoded instruction for storing in that instruction cache line, each at least one partially pre-decoded instruction having more bits than the corresponding received instruction and the unified cache being configured to use the instruction cache line in combination with its associated information portion to store said at least one partially pre-decoded instruction generated by the pre-decode circuitry; and further pre-decode circuitry associated with said further cache, and configured when the at least one partially pre-decoded instruction stored in one of said instruction cache lines is routed to the further cache for storage within at least one cache line of the further cache, to perform a further pre-decode operation on the at least one partially pre-decoded instruction in order to generate a corresponding at least one pre-decoded instruction for storage in the further cache.