发明名称 チョッパ式増幅回路
摘要 <p><P>PROBLEM TO BE SOLVED: To solve such a problem of a conventional chopper amplifier circuit that since the voltage in a period where chopper noise is not superimposed is held so as to remove the chopper noise synchronized with the chopper clock, and the voltage thus held is output, phase is shifted between the input voltage and the output voltage. <P>SOLUTION: The voltage demodulated by an output side switch circuit 18 is held by sample hold circuits 20, 22 which hold the value of a chopper clock before inversion until the chopper clock is inverted. Effects of chopper noise can be removed by the sample hold circuits 20, 22. Preferably, the amplifier circuit is configured by a pre-stage charge amplifier and a post-stage charge amplifier, and the holding time can be shortened. Output voltage fluctuation rate can be reduced by increasing the feedback resistance. A resistance ensuring a fluctuation rate of 5% or lower is preferably used. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5612501(B2) 申请公布日期 2014.10.22
申请号 JP20110022106 申请日期 2011.02.03
申请人 发明人
分类号 H03F1/32 主分类号 H03F1/32
代理机构 代理人
主权项
地址