发明名称 電荷層を軽減した集積回路構造およびこれを形成する方法
摘要 <p>A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.</p>
申请公布号 JP5610557(B2) 申请公布日期 2014.10.22
申请号 JP20130523205 申请日期 2011.07.28
申请人 发明人
分类号 H01L27/04;H01L21/336;H01L21/762;H01L21/822;H01L27/12;H01L29/786 主分类号 H01L27/04
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