发明名称 Method of manufacturing semiconductor device
摘要 A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.
申请公布号 US8865562(B2) 申请公布日期 2014.10.21
申请号 US201213601676 申请日期 2012.08.31
申请人 SK Hynix Inc. 发明人 Lee Duk Eui
分类号 H01L21/764;H01L27/115 主分类号 H01L21/764
代理机构 William Park & Associates Patent Ltd. 代理人 William Park & Associates Patent Ltd.
主权项 1. A method of manufacturing a semiconductor device, comprising: forming first gate lines and second gate lines over a semiconductor substrate, wherein each of the second gate lines has a greater width than each of the first gate lines; forming a first insulating layer surrounding top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines adjacent to each other and between the first gate lines; forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer; removing the first reaction region; forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer; and removing the second reaction regions so that a portion of each of the first and the second gate lines is exposed.
地址 Gyeonggi-do KR