| 摘要 |
Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device.;In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged. In the second discharge step, the clear signal (H_CLR) is set at the high level, and electric charges on floating nodes in each of the bistable circuits are discharged. |
| 主权项 |
1. A liquid crystal display device comprising:
a substrate that constitutes a display panel; a plurality of video signal lines which transmit video signals; a plurality of scanning signal lines which intersect the plurality of video signal lines; a plurality of pixel formation portions arranged in a matrix so as to correspond to the plurality of video signal lines and the plurality of scanning signal lines; a scanning signal line drive circuit that includes a shift register made of a plurality of bistable circuits which are provided so as to correspond to the plurality of scanning signal lines and sequentially output pulses based on a clock signal, and that selectively drives the plurality of scanning signal lines based on the pulses outputted from the shift register; a power supply circuit that generates, based on a power supply given from an outside, a scanning signal line selection potential as a potential for turning the scanning signal lines to a selected state, and a scanning signal line non-selection potential as a potential for turning the scanning signal lines to a non-selected state; a drive control unit that generates the clock signal, a clear signal for initializing states of the plurality of bistable circuits, and a reference potential as a potential serving as a reference of operations of the plurality of bistable circuits, and controls an operation of the scanning signal line drive circuit; and a power supply state detection unit that gives a predetermined power supply OFF signal to the drive control unit upon detecting an OFF state of the power supply, wherein the plurality of video signal lines, the plurality of scanning signal lines, the plurality of pixel formation portions, and the scanning signal line drive circuit are formed on the substrate, each of the bistable circuits includes:
an output node connected to the scanning signal line;an output control switching element in which a second electrode is given the clock signal, and a third electrode is connected to the output node;a first node connected to a first electrode of the output control switching element; anda first first-node control switching element in which a first electrode is given the clear signal, a second electrode is connected to the first node, and a third electrode is given the reference potential, the power supply circuit generates, as the scanning signal line selection potential, a first scanning signal line selection potential and a second scanning signal line selection potential, which are different from each other in change state of a potential level when the power supply is turned to an OFF state, the drive control unit:
sets a potential of the clock signal at the first scanning signal line selection potential or the scanning signal line non-selection potential;sets a potential of the clear signal at the second scanning signal line selection potential or the scanning signal line non-selection potential;sets the reference potential at the first scanning signal line selection potential or the scanning signal line non-selection potential; andupon receiving the power supply OFF signal, sequentially performs first discharge processing for setting the potential of the clock signal and the reference potential at the first scanning signal line selection potential, and second discharge processing for setting the potential of the clear signal at the second scanning signal line selection potential, and at a point of time when the second discharge processing is started, the first scanning signal line selection potential is equalized to a ground potential, and the second scanning signal line selection potential is maintained at a potential level at which the switching elements included in each of the bistable circuits are turned to an ON state. |
