发明名称 |
Method for forming impurity region of vertical transistor and method for fabricating vertical transistor using the same |
摘要 |
A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. |
申请公布号 |
US8859370(B2) |
申请公布日期 |
2014.10.14 |
申请号 |
US201313926575 |
申请日期 |
2013.06.25 |
申请人 |
SK Hynix Inc. |
发明人 |
Eun Yong Seok;Kim Tae Kyun;Rouh Kyong Bong;Park Eun Shil |
分类号 |
H01L21/336;H01L29/78;H01L29/66;H01L21/266;H01L27/108;H01L21/265 |
主分类号 |
H01L21/336 |
代理机构 |
William Park & Associates Patent Ltd. |
代理人 |
William Park & Associates Patent Ltd. |
主权项 |
1. A method for forming an impurity region of a vertical transistor, comprising:
preparing a semiconductor substrate having a first region and a second region; forming a first mask pattern on the semiconductor substrate; forming an impurity ion junction region on the semiconductor substrate by performing an ion implantation process using the first mask pattern; forming a material layer on the semiconductor substrate in which the impurity ion junction region is formed by using a material which is substantially equal to a material of the semiconductor substrate; forming a second mask pattern on the material layer, wherein the second mask pattern has an opening exposing a portion of the material layer covering the second region, wherein the second mask pattern is formed by an exposure process in such a state that a photomask used to form the first mask pattern is shifted in a horizontal direction; and forming the trench by etching the second region using the second mask pattern as an etching mask, wherein the etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. |
地址 |
Gyeonggi-do KR |