Biased bang-bang phase detector for clock and data recovery

摘要

An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

主权项

1. An apparatus comprising:
a plurality of phase detector circuits each configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition samples; and a summing circuit configured to generate an adjustment signal in response to said phase up and phase down signals of said plurality of phase detector circuits, wherein a sum of said phase up signals and a sum of said phase down signals are weighted to provide a bias to a phase adjustment, wherein said adjustment signal is based on a difference between said sum of said phase up signals weighted by a first control parameter and said sum of said phase down signals weighted by a second control parameter.