Liquid crystal display apparatus and source driving circuit thereof

摘要

A liquid crystal display apparatus includes a liquid crystal panel and a panel driving device. The panel driving device includes a timing control circuit, a gate driving circuit, and a source driving circuit. The source driving circuit includes a low voltage differential signal (LVDS) receiver, a driving voltage generator, and a controller. The LVDS receiver includes a plurality of receive circuits and a power saving control circuit. Each of the receive circuit performs level conversion upon a data LVDS to generate a logic signal, and operates in a selected one of a normal energy consuming mode and a power saving mode. The power saving control circuit controls the receive circuits to operate in the power saving mode when the power saving control circuit does not receive a power adjustment signal from the controller.

主权项

1. A liquid crystal display apparatus comprising:
a liquid crystal panel including a plurality of pixel units, each of the pixel units being disposed to receive a source driving voltage and a gate voltage; and a panel driving device including
a timing control circuit operable to generate a gate control signal and a data latch signal,a gate driving circuit coupled to the liquid crystal panel and the timing control circuit, the gate driving circuit receiving the gate control signal and generating the gate voltages for the pixel units according to the gate control signal, anda source driving circuit including
a low voltage differential signal (LVDS) receiver including:
a plurality of receive circuits, each disposed to receive a data LVDS and to perform level conversion upon the data LVDS to generate a logic signal, each of the receive circuits being operable in a selected one of a normal energy consuming mode and a power saving mode, anda power saving control circuit coupled to the receive circuits for controlling operation of the receive circuits in the power saving mode;a driving voltage generator disposed to receive a clock signal and coupled to the receive circuits so as to receive the logic signals therefrom, the driving voltage generator being operable to generate the source driving voltages for the pixel units in parallel by performing series-to-parallel conversion upon the logic signals according to multiple periods of high-low logic transitions of the clock signal, the driving voltage generator further outputting an END signal; anda controller coupled to the driving voltage generator so as to receive the END signal therefrom, coupled to the timing control circuit so as to receive the data latch signal therefrom, and operable to output a power adjustment signal from the data latch signal and to stop output of the power adjustment signal upon receipt of the END signal from the driving voltage generator, the controller being coupled to the power saving control circuit for providing the power adjustment signal thereto, the power saving control circuit controlling the receive circuits to operate in the power saving mode when the power saving control circuit does not receive the power adjustment signal from the controller.