| 摘要 |
A parallel computer synthesizes a digital map. The computer includes a first stage and a second stage. The first stage includes a background processor for generating a map background image and N overlay processors for generating first through Nth map overlay images of non-relocatable map features. First and second sets of interim buffers are alternately connected to the background processor and to the N overlay processors. The second stage includes a second stage processor connected to the output of the first and second sets of interim buffers for combining, according to a predetermined priority, the overlay images generated by the processors of the first stage to generate a composite map image. The second stage processor also generates a final map overlay image of relocatable features, and combines the composite map image with the overlay image of relocatable features to generate a display map image. A pair of output buffers is connected to the output of the second stage processor so that each buffer of the pair is alternately connected to the processor.
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