发明名称 Bias control for push-pull amplifier arrangement
摘要 An amplification stage comprising: a combiner to generate a sum input signal by combining a voltage signal with a DC bias voltage; a subtractor to generate a difference input signal by subtracting the voltage signal from the DC bias voltage; a first transistor for generating a first part of an amplifier output signal from the sum input signal; a second transistor for generating a second part of an amplifier output signal from the difference input signal; a combiner for combining the first and second parts of the amplifier output signal; a sensing circuit arranged to sense a current flowing in each of the first and second transistors; a control circuit arranged to determine the quiescent current of the first and second transistors in dependence on the sensed currents; and an adjustment circuit arranged to adjust the DC bias voltage in order to minimize variation in the quiescent current.
申请公布号 US8860510(B2) 申请公布日期 2014.10.14
申请号 US201313849080 申请日期 2013.03.22
申请人 Nujira Limited 发明人 Wimpenny Gerard
分类号 H03F3/26;H03F1/32;H03F1/02 主分类号 H03F3/26
代理机构 Kaplan Breyer Schwarz & Ottesen, LLP 代理人 Kaplan Breyer Schwarz & Ottesen, LLP
主权项 1. A Class AB push pull amplification stage arranged to receive a voltage signal to be amplified and a DC bias voltage, the amplification stage comprising: a combiner to generate a sum input signal by combining the voltage signal with the DC bias voltage; a subtractor to generate a difference input signal by subtracting the voltage signal from the DC bias voltage; a first transistor connected to receive the sum input signal and generate a first part of an amplifier output signal; a second transistor connected to receive the difference input signal and generate a second part of an amplifier output signal; a combiner for combining the first and second parts of the amplifier output signal; a sensing circuit arranged to sense a current flowing in each of the first and second transistors; a control circuit arranged to determine the quiescent current of the first and second transistors in dependence on the sensed currents; and an adjustment circuit arranged to adjust the DC bias voltage in order to minimise variation in the quiescent current.
地址 GB