SEMICONDUCTOR MEMORY DEVICE HAVING COMPRESSION TEST MODE

摘要

A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.

主权项

1. A semiconductor memory device comprising:
a memory unit comprising m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines; i test pads; a timing circuit to sequentially generate n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups; a compression circuit to compress data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode; and a signal distribution circuit to distribute signals output from the compression circuit among the i test pads in rotation; wherein m is a positive integer, n is a positive integer having a value of 1 or greater, i is a positive integer having a value of 1 or greater, and the integer n and the integer i are adjustable.