NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

摘要

In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

主权项

1. A non-volatile semiconductor memory device comprising:
a memory cell array comprising a plurality of memory blocks; a plurality of memory strings formed in each of the memory blocks, each memory string including a plurality of memory transistors connected in series, the plurality of memory transistors stacked in a direction perpendicular to a semiconductor substrate; a drain-side select transistor having a first end connected to a first end portion of each of the memory strings; a source-side select transistor having a first end connected to a second end portion of each of the memory strings; a plurality of word lines, each word line being commonly connected to the memory strings disposed in each of the memory blocks; a plurality of bit lines, each bit line being connected to second ends of the drain-side select transistors in respective memory blocks; a plurality of source lines provided in each of the memory blocks, each of the source lines being connected to a second end of the source-side select transistor; a drain-side select gate line provided to commonly connect gates of the drain-side select transistors; a source-side select gate line provided to commonly connect gates of the source-side select transistors; and a control circuit configured to control voltages supplied to the memory blocks, in performing a read operation of the memory transistor, the control circuit being configured to perform: supplying a first voltage to a selected word line connected to a selected memory transistor; supplying a second voltage to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage; supplying a third voltage to the bit line; supplying a fourth voltage lower than the third voltage to, among the source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block; and supplying a fifth voltage substantially the same as the third voltage to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.