发明名称 Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads
摘要 A SCAN chain architecture for each path in a circuit having combinational paths includes a control mechanism to control one or more flip flops and multiplexers to direct operational or test signals. Operational signals are sent along at least one combinational path to a pull-up/pull-down for at least one input/output pad and an operational voltage is recorded. Test signals are sent along at least one alternative path to an alternative input/output and a test voltage is recorded. The operational voltage is compared to the test voltage to identify a combinational path fault.
申请公布号 US2014304562(A1) 申请公布日期 2014.10.09
申请号 US201313872424 申请日期 2013.04.29
申请人 LSI CORPORATION 发明人 Tekumalla Ramesh C.;Sharma Vijay
分类号 G01R31/3185 主分类号 G01R31/3185
代理机构 代理人
主权项 1. A circuit, comprising: a test control logic having at least one input and at least one output; a first flip flop; a first multiplexer; and a first three-state gate, wherein: an output from the first flip flop is configured as an input to the first multiplexer;a first output of the at least one outputs of the test control logic is configured as an input to the first multiplexer; andthe output of the first multiplexer is a combinational path to a pull-up/pull-down of an input/output pad.
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