| 摘要 |
A method and apparatus for synchronizing a delay line to a reference clock. A delay line receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control signal. An injector receives a first edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the first edge has passed through the delay line, and in response, sends the injector a second trigger to send a second edge of the clock input signal to the delay line. An edge detector compares the timing of the first edge of the delay edge signal to a timing of the first edge of the reference edge signal. A control signal is sent to the delay line to decrease or increase the delay setting of the delay line based on the comparison. |
