Semiconductor memory apparatus

摘要

A semiconductor memory apparatus includes a synchronized signal generation circuit, a serial-to-parallel data conversion unit and a data storage region. The synchronized signal generation unit outputs one of a data input/output strobe signal and a delay locked clock signal as synchronized signals in response to a control signal in a write operation. The serial-to-parallel data conversion unit converts serial data into parallel data in response to the synchronized signals. The parallel data is stored in the data storage region.

主权项

1. A semiconductor memory apparatus comprising:
a serial-to-parallel data conversion unit configured to convert serial data into parallel data in response to a rising synchronized signal and a falling synchronized signal; a driver configured to drive a data input/output strobe signal and generate a first rising preliminary synchronized signal and a first falling preliminary synchronized signal; a preliminary synchronized signal generation unit configured to output a second rising preliminary synchronized signal and a second falling preliminary synchronized signal based on a delay locked clock signal at an enable timing of an active signal and a read signal or of the active signal and a write signal in a write operation in response to one or more of a frequency detection signal, a write latency signal, a read latency signal and a control signal; and a data synchronized signal generation unit configured to output the rising synchronized signal and the falling synchronized signal based on either the first rising and falling preliminary synchronized signals or the second rising or falling preliminary synchronized signals in response to the control signal.